Some data processing systems, such as those based on the Intel Pentium microprocessor chip, have portions that are not accessible to testing using normal commands of the system. Such a cache can be logically divided into three separate entities: a data random access memory (data RAM) for storing system data and instructions; a tag RAM for storing status data about the information stored in the data RAM; and control circuitry for overall operation of the cache. A test fixture for this cache must be able to fully test all circuit elements in all three of these entities in order to be sure of their quality and operability. The present invention is concerned with testing of the tag RAM independently of the other entities of the cache. The behavior of the cache is completely dependent of the status data stored in the tag RAM. If the bit locations in the tag RAM containing those status bits are defective, the cache will react in ways that are difficult to debug. In addition to testing the tag RAM for its independent operability, it is desirable to be able to enter data into it to test the cache and the system for their overall operability. However, while the storage locations in the data RAM are accessible and easy to test, the storage locations in the tag RAM, including those storing status data, are not readily accessible. All bits in a tag RAM word go to the cache controller and not onto the microprocessor system bus. Therefore, it is difficult to determine when an error occurs if an error is in the tag RAM or in the cache controller. Furthermore, certain data bit patterns do not occur in the tag RAM during normal system operation. For these reasons it is difficult to test the bit positions of the tag RAM themselves and to enter test patterns to test overall cache operation.